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cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-05610 rev. *e revised december 8, 2010 cy7c1012dv33 12-mbit (512 k 24) static ram features high speed ? t aa = 10 ns low active power ? i cc = 175 ma at 10 ns low cmos standby power ? i sb2 = 25 ma operating voltages of 3.3 0.3v 2.0v data retention automatic power down when deselected ttl compatible inputs and outputs available in pb-free standard 119-ball pbga functional description the cy7c1012dv33 is a high pe rformance cmos static ram organized as 512k words by 24 bits. each data byte is separately controlled by the individual chip selects (ce 1 , ce 2 , and ce 3 ). ce 1 controls the data on the i/o 0 ? i/o 7 , while ce 2 controls the data on i/o 8 ? i/o 15 , and ce 3 controls the data on the data pins i/o 16 ? i/o 23 . this device has an automatic power down feature that significantly reduces powe r consumption when deselected. writing the data bytes into the sram is accomplished when the chip select controlling that byte is low and the write enable input (we ) input is low. data on the respective input and output (i/o) pins is then written into the location specified on the address pins (a 0 ? a 18 ). asserting all of the chip selects low and write enable low writes all 24 bits of data into the sram. output enable (oe ) is ignored while in write mode. data bytes are also individually read from the device. reading a byte is accomplished when the ch ip select controlling that byte is low and write enable (we ) high, while output enable (oe ) remains low. under these conditions, the contents of the memory location specified on the address pins appear on the specified data input and output (i /o) pins. asserting all the chip selects low reads all 24 bits of data from the sram. the 24 i/o pins (i/o 0 ? i/o 23 ) are placed in a high impedance state when all the chip selects are high or when the output enable (oe ) is high during a read mode. for more infor- mation, see the truth table on page 8. logic block diagram column decoder row decoder sense amps input buffer 512k x 24 array i/o 0 ? i/o 7 oe i/o 8 ? i/o 15 ce 1 , ce 2 , ce 3 we i/o 16 ? i/o 23 control logic a (9:0) a (18:10) [+] feedback
cy7c1012dv33 document number: 38-05610 rev. *e page 2 of 12 selection guide description ?10 unit maximum access time 10 ns maximum operating current 175 ma maximum cmos standby current 25 ma pin configuration figure 1. 119-ball pbga ( top view) [1] 1 2 3 4 5 6 7 a ncaaaaanc b nc a a ce 1 aanc c i/o 12 nc ce 2 nc ce 3 nc i/o 0 d i/o 13 v dd v ss v ss v ss v dd i/o 1 e i/o 14 v ss v dd v ss v dd v ss i/o 2 f i/o 15 v dd v ss v ss v ss v dd i/o 3 g i/o 16 v ss v dd v ss v dd v ss i/o 4 h i/o 17 v dd v ss v ss v ss v dd i/o 5 j nc v ss v dd v ss v dd v ss nc k i/o 18 v dd v ss v ss v ss v dd i/o 6 l i/o 19 v ss v dd v ss v dd v ss i/o 7 m i/o 20 v dd v ss v ss v ss v dd i/o 8 n i/o 21 v ss v dd v ss v dd v ss i/o 9 p i/o 22 v dd v ss v ss v ss v dd i/o 10 r i/o 23 a ncncnc ai/o 11 t nc a a we aanc u nc a a oe aanc note 1. nc pins are not connected on the die. [+] feedback
cy7c1012dv33 document number: 38-05610 rev. *e page 3 of 12 maximum ratings exceeding maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature ................................. ?65 ? c to +150 ? c ambient temperature with power applied ............................................ ?55 ? c to +125 ? c supply voltage on v cc relative to gnd [2] ....?0.5v to +4.6v dc voltage applied to outputs in high-z state [2] .................................. ?0.5v to v cc + 0.5v dc input voltage [2] ............................... ?0.5v to v cc + 0.5v current into outputs (low) ........................................ 20 ma static discharge voltage............. ...............................>2001v (mil-std-883, method 3015) latch up current ..................................................... >200 ma operating range range ambient temperature v cc industrial ?40 ? c to +85 ? c3.3v ? 0.3v dc electrical characteristics over the operating range parameter description test conditions [3] ?10 unit min max v oh output high voltage v cc = min, i oh = ?4.0 ma 2.4 v v ol output low voltage v cc = min, i ol = 8.0 ma 0.4 v v ih input high voltage 2.0 v cc + 0.3 v v il [2] input low voltage ?0.3 0.8 v i ix input leakage current gnd < v i < v cc ?1 +1 ? a i oz output leakage current gnd < v out < v cc , output disabled ?1 +1 ? a i cc v cc operating supply current v cc = max, f = f max = 1/t rc i out = 0 ma cmos levels 175 ma i sb1 automatic ce power down current ?ttl inputs max v cc , ce > v ih v in > v ih or v in < v il , f = f max 30 ma i sb2 automatic ce power down current ?cmos inputs max v cc , ce > v cc ? 0.3v, v in > v cc ? 0.3v, or v in < 0.3v, f = 0 25 ma notes 2. v il (min) = ?2.0v and v ih (max) = v cc + 2v for pulse durations of less than 20 ns. 3. ce indicates a combination of all three chip enables. when active low, ce indicates the ce 1 or ce 2 , or ce 3 is low. when high, ce indicates the ce 1 , ce 2 , and ce 3 are high. [+] feedback
cy7c1012dv33 document number: 38-05610 rev. *e page 4 of 12 capacitance tested initially and after any design or process changes that may affect these parameters . parameter description test conditions max unit c in input capacitance t a = 25 ? c, f = 1 mhz, v cc = 3.3v 8 pf c out i/o capacitance 10 pf thermal resistance tested initially and after any design or process changes that may affect these parameters. parameter description test conditions 119-ball pbga unit ? ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 inch, four layer printed circuit board 20.31 ? c/w ? jc thermal resistance (junction to case) 8.35 ? c/w figure 2. ac test loads and waveforms [4] 90% 10% 3.0v gnd 90% 10% all input pulses 3.3v output 5 pf* (a) (b) r1 317 ? r2 351 ? fall time:> 1v/ns (c) output 50 ? z 0 = 50 ? v th = 1.5v 30 pf* * capacitive load consists of all components of the test environment rise time > 1v/ns *including jig and scope note 4. valid sram operation does not occur until the power supplies have reached the minimum operating v dd (3.0v). 100 ? s (t power ) after reaching the minimum operating v dd , normal sram operation begins including reduction in v dd to the data retention (v ccdr , 2.0v) voltage. [+] feedback
cy7c1012dv33 document number: 38-05610 rev. *e page 5 of 12 ac switching ch aracteristics over the operating range [5] parameter description ?10 unit min max read cycle t power [6] v cc (typical) to the first access 100 ? s t rc read cycle time 10 ns t aa address to data valid 10 ns t oha data hold from address change 3 ns t ace ce active low to data valid [3] 10 ns t doe oe low to data valid 5 ns t lzoe oe low to low z [7] 1ns t hzoe oe high to high z [7] 5ns t lzce ce active low to low z [3, 7] 3ns t hzce ce deselect high to high z [3, 7] 5ns t pu ce active low to power up [3, 8] 0ns t pd ce deselect high to power down [3, 8] 10 ns write cycle [9, 10] t wc write cycle time 10 ns t sce ce active low to write end [3] 7ns t aw address setup to write end 7 ns t ha address hold from write end 0 ns t sa address setup to write start 0 ns t pwe we pulse width 7 ns t sd data setup to write end 5.5 ns t hd data hold from write end 0 ns t lzwe we high to low z [7] 3ns t hzwe we low to high z [7] 5ns notes 5. test conditions assume signal transition time of 3 ns or less , timing reference levels of 1.5v, and input pulse levels of 0 t o 3.0v. test conditions for the read cycle use output loading as shown in part a) of figure 2 , unless specified otherwise. 6. t power gives the minimum amount of time that the power supply is at typical v cc values until the first memory access is performed. 7. t hzoe , t hzce , t hzwe , t lzoe , t lzce , and t lzwe are specified with a load capacitance of 5 pf as in part (b) of figure 2 . transition is measured ? 200 mv from steady state voltage. 8. these parameters are guaranteed by design and are not tested. 9. the internal write time of the memory is defined by the overlap of ce 1 or ce 2 or ce 3 low and we low. chip enables must be active and we must be low to initiate a write. the transition of any of these signals terminate the writ e. the input data setup and hold timing are referenced to the leading edge of the signal that terminates the write. 10. the minimum write cycle time for write cycle no. 3 (we controlled, oe low) is the sum of t hzwe and t sd . [+] feedback
cy7c1012dv33 document number: 38-05610 rev. *e page 6 of 12 data retention characteristics over the operating range parameter description conditions [3] min typ max unit v dr v cc for data retention 2 v i ccdr data retention current v cc = 2v, ce > v cc ? 0.2v, v in > v cc ? 0.2v or v in < 0.2v 25 ma t cdr [11] chip deselect to data retention time 0ns t r [12] operation recovery time t rc ns data retention waveform switching waveforms figure 3. read cycle no. 1 [13, 14] figure 4. read cycle no. 2 (oe controlled) [3, 14, 15] 3.0v 3.0v t cdr v dr > 2v data retention mode t r ce v cc previous data valid data valid rc t aa t oha t rc address data out 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t pd t hzce oe ce address data out v cc supply current high impedance i cc i sb notes 11. tested initially and after any design or proce ss changes that may affect these parameters. 12. full device operation requires linear v cc ramp from v dr to v cc(min) > 50 ? s or stable at v cc(min) > 50 ? s. 13. device is continuously selected. oe , ce = v il . 14. we is high for read cycle. 15. address valid before or similar to ce transition low. [+] feedback
cy7c1012dv33 document number: 38-05610 rev. *e page 7 of 12 figure 5. write cycle no. 1 (ce controlled) [3, 16, 17] figure 6. write cycle no. 2 (we controlled, oe high during write) [3, 16, 17] figure 7. write cycle no. 3 (we controlled, oe low) [3, 17] switching waveforms (continued) t wc data valid t aw t sa t pwe t ha t hd t sd t sce t sce ce we data i/o address t hd t sd t pwe t sa t ha t aw t sce t wc t hzoe data in valid ce address we data i/o oe note 18 data valid t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe ce address we data i/o note 18 notes 16. data i/o is high impedance if oe = v ih . 17. if ce goes high simultaneously with we going high, the output remains in a high impedance state. 18. during this period, the i/os are in output state. do not apply input signals. [+] feedback
cy7c1012dv33 document number: 38-05610 rev. *e page 8 of 12 truth table ce 1 ce 2 ce 3 oe we i/o 0 ? i/o 7 i/o 8 ? i/o 15 i/o 16 ? i/o 23 mode power h h h x x high z high z high z power down standby (i sb ) l h h l h data out high z high z read active (i cc ) h l h l h high z data out high z read active (i cc ) h h l l h high z high z data out read active (i cc ) llllhfull data outfull data outfull data outread active (i cc ) l h h x l data in high z high z write active (i cc ) h l h x l high z data in high z write active (i cc ) h h l x l high z high z data in write active (i cc ) l l l x l full data in full data in full data in write active (i cc ) l l l h h high z high z high z selected, outputs disabled active (i cc ) [+] feedback
cy7c1012dv33 document number: 38-05610 rev. *e page 9 of 12 ordering information speed (ns) ordering code package name package type operating range 10 CY7C1012DV33-10BGXI 51-85115 119-ball plastic ball grid array (14 x 22 x 2.4 mm) (pb-free) industrial ordering code definitions temperature range: i = industrial package type: bgx = 119-ball pbga (pb-free) speed: 10 ns voltage range: v33 = 3 v to 3.6 v d = c9, 90 nm technology 012 = 12-mbit density 1 = fast asynchronous sram family technology code: c = cmos 7 = sram cy = cypress c cy 1 - 10 bgx 7 012 d i v33 [+] feedback
cy7c1012dv33 document number: 38-05610 rev. *e page 10 of 12 package diagram figure 8. 119-ball pbga (14 22 2.4 mm) 51-85115 *c [+] feedback
cy7c1012dv33 document number: 38-05610 rev. *e page 11 of 12 document history page document title: cy7c1012dv33 12-mbit (512 k 24) static ram document number: 38-05610 rev. ecn no. orig. of change submission date description of change ** 250650 syt see ecn new data sheet *a 469517 nxr see ecn converted from advance information to preliminary corrected typo in the document title removed ?10 and ?12 speed bins from product offering changed j7 ball of bga from dnu to nc removed industrial operating range from product offering included the maximum ratings for static discharge voltage and latch up current on page 3 changed i cc(max) from 220 ma to 150 ma changed i sb1(max) from 70 ma to 30 ma changed i sb2(max) from 40 ma to 25 ma specified the overshoot spec ification in footnote 1 updated the truth table updated the ordering information table *b 499604 nxr see ecn added note 1 for nc pins changed i cc specification from 150 ma to 185 ma updated test condition for i cc in dc electrical characteristics table added note for t ace , t lzce , t hzce , t pu , t pd , and t sce in ac switching characteristics table on page 4 *c 1462585 vkn see ecn converted from preliminary to final updated block diagram changed i cc specification from 185 ma to 225 ma updated thermal specs *d 2604677 vkn/pyrs 11/12/08 removed commercial ope rating range, added industrial operating range removed 8 ns speed bin, added 10 ns speed bin, modified footnote# 3 *e 3104943 aju 12/08/2010 added ordering code definitions . updated package diagram . [+] feedback
cy7c1012dv33 ? cypress semiconductor corporation, 2004-2010. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreemen t with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support syst ems where a malfunction or failure may reas onably be expected to result in significa nt injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and international treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or impl ied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress re serves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. document number: 38-05610 rev. *e revised december 8, 2010 page 12 of 12 all product and company names mentioned in this document are the trademarks of their respective holders . sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress.com/sales. products psoc psoc.cypress.com clocks & buffers clocks.cypress.com wireless wireless.cypress.com memories memory.cypress.com image sensors image.cypress.com psoc solutions general psoc.cypress.com/solutions low power/low voltage psoc.cypress.com/low-power precision analog psoc.cypress.com/precision-analog lcd drive psoc.cypress.com/lcd-drive can 2.0b psoc.cypress.com/can usb psoc.cypress.com/usb [+] feedback

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